Device-Algorithm Co-Optimization of TiOₓ-based Resistive Switching Devices

Abstract

The rapid advancement of artificial intelligence (AI) and growing demand for high-performance computing have exposed key limitations in von Neumann architectures, particularly energy inefficiency and data movement bottlenecks. Resistive Random Access Memory (RRAM) has emerged as a promising candidate for next-generation memory technologies, offering non-volatility, high integration density, and the potential for energy-efficient Compute-In-Memory (CIM) architectures. This thesis focuses on the development and optimization of TiOₓ-based RRAM devices, with a particular emphasis on their application in CIM systems. The work begins with a comprehensive exploration of the device characteristics of TiOₓ-based RRAM, including the influence of electrode materials, oxygen stoichiometry, and physical dimensions on device performance. Through interface engineering and material stack optimization, we achieve significant improvements in forming voltage, endurance, and retention, enabling low-power operation and high reliability. The optimized devices exhibit stable bipolar switching behavior with forming voltages below 1.5 V and operation currents under 100 μA, making them suitable for integration with advanced CMOS technologies. Building on the optimized device performance, we propose a state-aware multi-bit programming algorithm that significantly reduces the number of programming steps and improves the efficiency of multi-bit operations. The algorithm leverages the state-dependent conductance modulation of RRAM devices, enabling precise control over resistance states and mitigating the effects of fast relaxation and retention loss. Additionally, we introduce an electrical annealing method to further enhance the long-term stability of multi-bit programming, demonstrating its effectiveness in extending the refresh period for CIM applications. To bridge the gap between device-level optimization and system-level implementation, we present a back-end-of-line (BEOL) integration process for TiOₓ-based RRAM devices on CMOS chips. The integration process is validated through the successful fabrication and characterization of 1T1R arrays, demonstrating reliable resistive switching behavior and compatibility with existing CMOS technologies. This integration paves the way for the development of RRAM-based CIM macros, which combine RRAM arrays with peripheral circuits for high-performance AI computing. Finally, we discuss future directions for device optimization, hardware-aware CIM design, and system-level integration. Key challenges include reducing programming current, improving retention stability, and developing reconfigurable CIM architectures for emerging AI workloads. The insights and methodologies developed in this thesis provide a foundation for the continued advancement of RRAM technologies and their integration into next-generation computing systems. In summary, this thesis contributes to the field of RRAM-based CIM by addressing critical challenges in device optimization, multi-bit programming, and CMOS integration. The proposed solutions not only enhance the performance and reliability of RRAM devices but also provide a pathway for their practical implementation in energy-efficient AI hardware.